Output drivers in transmitting devices have edge placement inaccuracies due to static timing offsets and dynamic timing errors. Static timing offsets are caused, for example, by transistor mismatches, skew in the clock distribution tree, unequal parasitics, slew rate variation between pull-up and pull-down circuits, packaging differences, etc. Dynamic timing errors are caused, for example, by intersymbol interference (ISI), simultaneous switching output (SSO) noise, clock jitter, etc. Due to the above effects, transmitting devices with multiple outputs have pin-to-pin skew. This skew or misalignment in the outputs significantly contributes to the overall timing inaccuracy of a system utilizing the outputs and therefore reduces the maximum frequency at which the interconnection can operate. This pin-to-pin skew also limits the production yield of the transmitting device, as devices having excessive skew may be unacceptable for use. Thus, a method and apparatus for reducing the pin-to-pin skew is needed to allow increased performance, including operation at higher frequencies, and increased production yields.